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CPU Model |
A |
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F(flags) |
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B |
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C |
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D |
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E |
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H |
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L |
Stack Pointer |
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I |
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R |
Interrupt and Refresh |
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IX |
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Index |
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IY |
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Index |
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SP |
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Stack Pointer |
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PC |
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Program Counter |
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Flags |
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Logic Operators |
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C |
carry |
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Opcode |
Description |
Store |
Flags | |
N |
add/subtract |
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AND |
Acc AND memory/register |
Acc |
S,Z,H,P/V | |
P/V |
parity/overflow |
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* |
Unused |
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OR |
Acc OR memory/register |
Acc |
S,Z,H,P/V | |
H |
half carry |
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* |
Unused |
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XOR |
Acc EOR memory/register |
Acc |
S,Z,H,P/V | |
Z |
zero |
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S |
sign |
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Addressing Mode |
Form |
Description |
Implied
|
Opcode reg,(HL) |
HL is address of memory location of data |
Immediate |
OpCode reg, #1BN |
1BN is Data |
OpCode regpair, #2BN |
2BN is Data | |
Direct
|
OpCode A, (1BN) |
1BN is memory location of Data |
OpCode regpair, (2BN) |
2BN is memory location of Data | |
Program Relative |
OpCode flag, 1BN |
1BN plus PC is memory location of Data |
Register Indirect |
OpCode (regpair) |
regpair is address of memory location of Data |
Indexed |
OpCode reg, (Ireg+1BN) |
Ireg+1BN is address of memory location of Data |
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Exchange and Alternative Register Set | |
Instruction |
Description |
EX AF,A`F` |
Exchange contents of AF and A`F` |
EXX |
Exchange contents of BC,DE and HL with BC`,DE` and HL` |
EX DE,HL |
Exchange contents |
EX (SP),HL |
Exchange top two bytes of stack with contents of HL |
EX (SP),IX/IY |
Exchange top two bytes of stack with contents of IX or IY |
Jump on Status Flag |
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Flag |
Description |
Branch if Set |
Branch if Not Set | |
C
|
Carry -greater/equal |
JR C, disp |
JR NC, disp | |
Z
|
Zero - equal |
JR Z, disp |
JR NZ, disp | |
disp = displacement added to PC | ||||